1. Field of the Invention
The present invention relates to control of a cache memory in a multiprocessor system, and more particularly to switching of cache control protocols.
2. Description of the Related Art
Conventionally, two kinds of cache control protocols have been used in a multiprocessor system. One is a store-in scheme in which only data in a cache memory is updated at a data update and the updated data is reflected in a main memory when a pertinent data portion in the cache memory is written back to the main memory. The other is a store-through scheme in which updated data is also reflected in a main memory simultaneously with reflection of the updated data in a cache memory at a data update.
Under a multiprocessor environment, the store-in scheme requires only a few number of accesses to a main memory since the updated data is reflected only in a cache at the data update. However, when another processor intends to update data in the same data area as that of the updated data, the data update is performed after the data in the data area is written back from a cache having that the newest updated data and transferred to a cache held by the other processor. As a result, data is frequently transferred among caches at update of a main memory area shared among a plurality of processors, which causes deteriorated performance.
On the other hand, in the store-through scheme, since the data update is reflected not only in a cache in a processor concerned but also in a main memory at each data update, the number of accesses to a main memory is significantly increased under a multiprocessor environment. This leads to a delay in response to memory access and thus deteriorated performance.
In view of these circumstances, a multiprocessor system has been proposed which switches during running a cache control protocol of the store-through scheme which updates a main memory simultaneously with the update of a cache memory and a cache control protocol of the store-in scheme which does not update a main memory at the update of a cache memory to each other.
For example, in JP-2-226449A and JP-3-210645A, each page in a main memory is provided with a flag for indicating whether the page is shared among a plurality of processors such that the store-through scheme is employed at an access to shared pages and the store-in scheme is employed at an access to other pages. Additionally, in JP-3-40046A, each page or each segment in a memory is provided with a descriptor for indicating a store-in or store-through attribute such that a cache control protocol is switched during running between the store-through scheme and the store-in scheme depending on the descriptor of the accessed page or segment.
According to the aforementioned prior arts, drawbacks can be overcome for each of the store-in and store-through schemes. Specifically, it is possible to suppress moves of data for a shared memory area among caches while the number of accesses to a main memory is reduced under a multiprocessor environment, thereby allowing improvement in performance.
However, any of the prior arts switches cache control protocols on the basis of an area to be accessed. When cache control protocols are switched on the basis of the area to be accessed, there exists a problem that an architecture requires change which causes incompatibility with conventional devices. Specifically, when cache control protocols are changed on the basis of the area to be accessed, as described in each of the aforementioned official gazettes, it is required that a segment descriptor or page descriptor is used to indicate an attribute of the area to be accessed or a flag is added for discriminating between the store-in scheme and store-through scheme. However, since and the segment descriptor or the like is defined in terms of structure by an architecture, causing the need for change of the architecture itself occurs.
It is thus an object of the present invention to provide a method of controlling a cache memory capable of switching during running cache control protocols without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed, and an apparatus therefor.
A method of controlling a cache memory in a multiprocessor system according to the present invention detects whether a software module which accesses stored data via a cache memory matches the software module preset as one which accesses a shared memory area on a main memory, and switches cache control protocols depending on the detection result. Specifically, control is performed in a store-through scheme cache control protocol which updates the main memory simultaneously with the update of the cache memory when the software modules is a software module which accesses the shared memory area on the main memory, otherwise control is performed in a store-in scheme cache control protocol which does not update the main memory at the update of the cache memory.
The multiprocessor system of the present invention is characterized in that it comprises, in each processor, module detecting means for detecting execution of a in a software module to access a shared memory area on a main memory, and means for controlling memory access executed in a software module detected by the module detecting means in the store-through scheme cache control protocol or for controlling memory access in other than the aforementioned case in the store-in scheme cache control protocol.
In this manner, the cache control protocols are switched by detecting whether a software module which attempts to access stored data is a preset software module for accessing a shared memory area on a main memory, thereby allowing switching of the cache control protocols during running without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of example.